SN74AHC16374

Name: SN74AHC16374
Brand: TI
SKU: SN74AHC16374
Price: 0.5 USD

現行

具有 3 態輸出的 16 位元邊緣觸發 D 型正反器

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產品規格表

document-pdfAcrobat 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs datasheet (Rev. G) (英文)

SN74AHC16374

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

16

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

110

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

40

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

16

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

110

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

40

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Members of the Texas Instruments Widebus^TM Family
EPIC^TM (Enhanced-Performance Implanted CMOS) Process
Operating Range 2-V to 5.5-V V_CC
3-State Outputs Drive Bus Lines Directly
Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

Members of the Texas Instruments Widebus^TM Family
EPIC^TM (Enhanced-Performance Implanted CMOS) Process
Operating Range 2-V to 5.5-V V_CC
3-State Outputs Drive Bus Lines Directly
Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The 'AHC16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AHC16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AHC16374 is characterized for operation from -40°C to 85°C.

The 'AHC16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AHC16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AHC16374 is characterized for operation from -40°C to 85°C.

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