SN74ALS990
- 3-State I/O-Type Read-Back Inputs
- Bus-Structured Pinout
- True Logic Outputs
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs
This 8-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus.
The eight latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
Read back is provided through the output-enable () input. When
is taken low, the data present at
the output of the data latches is allowed to pass back onto the input
data bus. When
is taken high,
the output of the data latches is isolated from the D inputs.
does not affect the internal
operation of the latches; however, precautions should be taken not to
create a bus conflict.
The SN74ALS990 is characterized for operation from 0°C to 70°C.
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
PDIP (N) | 20 | Ultra Librarian |
SOIC (DW) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點