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D 型正反器

SN74ALVCH16821

現行

具有 3 態輸出的 3.3-V 20 位元匯流排介面正反器

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產品規格表

SN74ALVCH16821

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 20 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 20 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

This 20-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 20-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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類型 標題 日期
* Data sheet SN74ALVCH16821 datasheet (Rev. F) 2004年 8月 30日
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74ALVCH16821 IBIS Model (Rev. A)

SCEM038A.ZIP (10 KB) - IBIS Model
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SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
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