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邏輯和電壓轉換
電壓轉換器及電平移位器
方向控制電壓轉換器

SN74AVC8T245

現行

具有可配置電壓電平移位變化與 3 態輸出的 8 位元雙電源供應匯流排收發器

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產品規格表

現在提供此產品的更新版本

open-in-new 比較替代產品
可直接投入的替代產品，相較於所比較的裝置，具備升級功能
SN74AXC8T245 現行 8 位元雙電源匯流排收發器 Pin-to-pin upgrade with a wider voltage range and improved performance
最新 TXV0108-Q1 現行 車用雙電源方向控制八通道電壓轉換器 Improved timing specs such as rise/fall time, skew, and propagation delay.
功能與所比較的裝置相似
最新 TXV0106-Q1 現行 Automotive dual-supply fixed-direction six-channel voltage translator 6 channel device with improved timing specs such as rise/fall time, skew, and propagation delay.

SN74AVC8T245

現行
產品規格表 立即訂購

產品詳細資料

Technology family AVC Applications RGMII Bits (#) 8 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 320 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 25 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AVC Applications RGMII Bits (#) 8 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 320 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 25 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 TVSOP (DGV) 24 32 mm² 5 x 6.4 VQFN (RHL) 24 19.25 mm² 5.5 x 3.5
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control inputs V IH/V IL levels are referenced to V CCA voltage
  • V CC isolation feature – if either V CC input is at GND, all I/O ports are in the high-impedance state
  • I off supports partial power-down mode operation
  • Fully configurable dual-rail design allows each port to operate over the full 1.4-V to 3.6-V power-supply range
  • I/Os are 4.6-V tolerant
  • Maximum data rates:
    • 170Mbps (V CCA  < 1.8 V or V CCB  < 1.8 V)
    • 320Mbps (V CCA  ≥ 1.8 V and V CCB ≥ 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control inputs V IH/V IL levels are referenced to V CCA voltage
  • V CC isolation feature – if either V CC input is at GND, all I/O ports are in the high-impedance state
  • I off supports partial power-down mode operation
  • Fully configurable dual-rail design allows each port to operate over the full 1.4-V to 3.6-V power-supply range
  • I/Os are 4.6-V tolerant
  • Maximum data rates:
    • 170Mbps (V CCA  < 1.8 V or V CCB  < 1.8 V)
    • 320Mbps (V CCA  ≥ 1.8 V and V CCB ≥ 1.8 V)

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC8T245 is optimized to operate with V CCA/V CCB set at 1.4 V to 3.6 V. The device is operational with V CCA and V CCB as low as 1.2 V. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V CCB. V CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVC8T245 is designed so that the control pins (DIR and OE) are supplied by V CCA.

The SN74AVC8T245 is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.

The V CC isolation feature allows both ports to be in the high-impedance state when either V CC input is at GND.

To put the device into the high-impedance state during power up or power down, tie OE to V CC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC8T245 is optimized to operate with V CCA/V CCB set at 1.4 V to 3.6 V. The device is operational with V CCA and V CCB as low as 1.2 V. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V CCB. V CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVC8T245 is designed so that the control pins (DIR and OE) are supplied by V CCA.

The SN74AVC8T245 is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.

The V CC isolation feature allows both ports to be in the high-impedance state when either V CC input is at GND.

To put the device into the high-impedance state during power up or power down, tie OE to V CC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
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類型 標題 日期
* Data sheet SN74AVC8T2458-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. K) PDF | HTML 2023年 11月 8日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
EVM User's guide TXV010xEVM Evaluation Module User's Guide PDF | HTML 2024年 2月 5日
Application note Overcoming Design Challenges - Implementing High Performance Interfaces PDF | HTML 2023年 12月 12日
Application brief Translate Voltages for RGMII (Rev. A) PDF | HTML 2021年 8月 6日
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 2021年 7月 30日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

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模擬型號

SN74AVC8T245 IBIS Model (Rev. A)

SCEM415A.ZIP (65 KB) - IBIS Model
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TSSOP (PW) 24 Ultra Librarian
TVSOP (DGV) 24 Ultra Librarian
VQFN (RHL) 24 Ultra Librarian
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