SN74CBTLV3125

Name: SN74CBTLV3125
Brand: TI
SKU: SN74CBTLV3125
Price: 0.135 USD

現行

具有關機保護功能的 3.3-V、1:1 (SPST)、4 雙通道 FET 匯流排開關

立即訂購

產品規格表

document-pdfAcrobat SN74CBTLV3125 datasheet (Rev. J) (英文)

SN74CBTLV3125

現行

產品規格表

立即訂購

產品詳細資料

Configuration

1:1 SPST

Number of channels

4

Power supply voltage - single (V)

2.5, 3.3

Protocols

Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART

Ron (typ) (Ω)

5

ON-state leakage current (max) (µA)

1

Bandwidth (MHz)

200

Operating temperature range (°C)

-40 to 85

Input/output continuous current (max) (mA)

128

Rating

Catalog

Drain supply voltage (max) (V)

3.6

Supply voltage (max) (V)

3.6

Configuration

1:1 SPST

Number of channels

4

Power supply voltage - single (V)

2.5, 3.3

Protocols

Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART

Ron (typ) (Ω)

5

ON-state leakage current (max) (µA)

1

Bandwidth (MHz)

200

Operating temperature range (°C)

-40 to 85

Input/output continuous current (max) (mA)

128

Rating

Catalog

Drain supply voltage (max) (V)

3.6

Supply voltage (max) (V)

3.6

SOIC (D)

14

51.9 mm² 8.65 x 6

SSOP (DBQ)

16

29.4 mm² 4.9 x 6

TSSOP (PW)

14

32 mm² 5 x 6.4

TVSOP (DGV)

14

23.04 mm² 3.6 x 6.4

VQFN (RGY)

14

12.25 mm² 3.5 x 3.5

Standard ’125-Type Pinout
5- Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Standard ’125-Type Pinout
5- Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE\) input is high.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE\) input is high.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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檢視所有 18

	類型	標題		日期
*	Data sheet	SN74CBTLV3125 datasheet (Rev. J)		2003年 10月 10日
	Application note	Selecting the Correct Texas Instruments Signal Switch (Rev. E)	PDF \| HTML	2022年 6月 2日
	Application note	Multiplexers and Signal Switches Glossary (Rev. B)	PDF \| HTML	2021年 12月 1日
	Application brief	Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C)	PDF \| HTML	2021年 1月 6日
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)		2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)		2007年 1月 16日
	More literature	Digital Bus Switch Selection Guide (Rev. A)		2004年 11月 10日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日
	User guide	Signal Switch Data Book (Rev. A)		2003年 11月 14日
	Application note	Bus FET Switch Solutions for Live Insertion Applications		2003年 2月 7日
	Application note	Texas Instruments Little Logic Application Report		2002年 11月 1日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002年 8月 29日
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002年 6月 13日
	User guide	CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B)		1998年 12月 1日

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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.

使用指南: PDF