SN74HC373A

Name: SN74HC373A
Brand: TI
SKU: SN74HC373A
Price: 0.223 USD

現行

具有 3 態輸出的八路透明 D 型鎖存器

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產品規格表

document-pdfAcrobat Octal Transparent D-Type Latch With 3-State Outputs datasheet (英文)

SN74HC373A

現行

產品規格表

立即訂購

產品詳細資料

Technology family

HC

Operating temperature range (°C)

to

Rating

Catalog

Technology family

HC

Operating temperature range (°C)

to

Rating

Catalog

SOP (NS)

20

98.28 mm² 12.6 x 7.8

Eight High-Current Latches in a Single Package
High-Current 3-State True Outputs Can Drive up to 15 LSTTL Loads
Full Parallel Access for Loading

Eight High-Current Latches in a Single Package
High-Current 3-State True Outputs Can Drive up to 15 LSTTL Loads
Full Parallel Access for Loading

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN74HC373A are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

An output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN74HC373A are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

An output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

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