SN74HCS264-Q1

Name: SN74HCS264-Q1
Brand: TI
SKU: SN74HCS264-Q1
Price: 0.139 USD

現行

車用 8 位元平行輸出序列移位暫存器

立即訂購

產品規格表

document-pdfAcrobat SN74HCS264-Q1 Automotive 8-Bit Parallel-Out Serial Shift Registers datasheet (英文)

SN74HCS264-Q1

現行

產品規格表

立即訂購

產品詳細資料

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

HCS

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (MHz)

62

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

HCS

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (MHz)

62

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

SOIC (D)

14

51.9 mm² 8.65 x 6

TSSOP (PW)

14

32 mm² 5 x 6.4

AEC-Q100 Qualified for automotive applications:
- Device temperature grade 1: –40°C to +125°C, T_A
- Device HBM ESD Classification Level 2
- Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
7.8-mA output drive at 6 V

AEC-Q100 Qualified for automotive applications:
- Device temperature grade 1: –40°C to +125°C, T_A
- Device HBM ESD Classification Level 2
- Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
7.8-mA output drive at 6 V

The device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. All inputs include Schmitt-trigger architecture, adding noise margin and eliminating any input transition rate requirement. Clocking occurs on the low-to-high-level transition of CLK.

Upon a clock trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The outputs are inverted from the data stored.

The device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. All inputs include Schmitt-trigger architecture, adding noise margin and eliminating any input transition rate requirement. Clocking occurs on the low-to-high-level transition of CLK.

Upon a clock trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The outputs are inverted from the data stored.

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