SN74HCT595-Q1
- AEC-Q100 qualified for automotive applications:
- Device temperature grade 1:
- –40°C to +125°C, TA
- Device HBM ESD Classification Level 2
- Device CDM ESD Classifcation Level C6
- Device temperature grade 1:
- LSTTL input logic compatible
- VIL(max) = 0.8 V, VIH(min) = 2 V
- CMOS input logic compatible
- II ≤ 1 µA at VOL, VOH
- 4.5 V to 5.5 V operation
- Supports fanout up to 10 LSTTL loads
- Shift register has direct clear
The SN74HCT595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH) are not impacted by the operation of the OE input.
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點