SN74LS93

Name: SN74LS93
Brand: TI
SKU: SN74LS93
Price: 1 USD

現行

4 位元二進位計數器

立即訂購

產品規格表

document-pdfAcrobat Decade, Divide-by-Twelve And Binary Counters datasheet (Rev. A) (英文)

SN74LS93

現行

產品規格表

立即訂購

產品詳細資料

Function

Counter

Bits (#)

4

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Function

Counter

Bits (#)

4

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

14

181.42 mm² 19.3 x 9.4

SOIC (D)

14

51.9 mm² 8.65 x 6

'90A, 'LS90 . . . Decade Counters
'92A, 'LS92 . . . Divide By-Twelve Counters
'93A, 'LS93 . . . 4-Bit Binary Counters

TYPES	TYPICAL POWER DISSIPATION
'90A	145 mW
'92A, '93A	130 mW
'LS90, 'LS92, 'LS93	45 mW

'90A, 'LS90 . . . Decade Counters
'92A, 'LS92 . . . Divide By-Twelve Counters
'93A, 'LS93 . . . 4-Bit Binary Counters

TYPES	TYPICAL POWER DISSIPATION
'90A	145 mW
'92A, '93A	130 mW
'LS90, 'LS92, 'LS93	45 mW

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93.

All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications.

To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the Q_A output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the Q_D output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output Q_A.

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93.

All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications.

To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the Q_A output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the Q_D output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output Q_A.

filter

尋找其它計數器

下載