SN74LV175A

Name: SN74LV175A
Brand: TI
SKU: SN74LV175A
Price: 0.107 USD

現行

具有清除功能的四路 D 型正反器

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產品規格表

document-pdfAcrobat SN74LV175A Quadruple D-Type Flip-Flops With Clear datasheet (Rev. J) (英文) PDF | HTML

SN74LV175A

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

Technology family

LV-A

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

IOL (max) (mA)

IOH (max) (mA)

-12

Supply current (max) (µA)

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

Technology family

LV-A

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

IOL (max) (mA)

IOH (max) (mA)

-12

Supply current (max) (µA)

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

59.4 mm² 9.9 x 6

79.56 mm² 10.2 x 7.8

32 mm² 5 x 6.4

23.04 mm² 3.6 x 6.4

V CC operation of 2 V to 5.5
Maximum t pd of 7.5 ns at 5 V
Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
I off supports partial-power-down mode operation
Supports mixed-mode voltage operation on all ports
Contains four flip-flops with double-rail outputs

V CC operation of 2 V to 5.5
Maximum t pd of 7.5 ns at 5 V
Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
I off supports partial-power-down mode operation
Supports mixed-mode voltage operation on all ports
Contains four flip-flops with double-rail outputs

The SN74LV175A device is quadruple D-type flip-flops designed for 2 V to 5.5 V V CC operation. These devices have a direct clear ( CLR) input and feature complementary outputs from each flip-flop.

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	類型	標題		日期
*	Data sheet	SN74LV175A Quadruple D-Type Flip-Flops With Clear datasheet (Rev. J)	PDF \| HTML	2023年 3月 23日
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	2022年 12月 15日