SN74LV393A
- VCC operation of 2 V to 5.5 V
- Max tpd of 10 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
- Ioff supports Partial-Power-Down-Mode operation
- Dual 4-bit binary counters with individual clocks
- Direct clear for each 4-bit counter
- Can significantly improve system densities by reducing counter package count by 50 percent
- Latch-Up performance exceeds 100 mA per JESD 78, Class II
The ’LV393A devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices are designed for 2 V to 5.5 V VCC operation.
技術文件
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檢視所有 1 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN74LV393A Dual 4-Bit Binary Counters datasheet (Rev. E) | PDF | HTML | 2023年 3月 16日 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
參考設計
TIPD169 — 16 位元 1 MSPS 多工處理資料採集參考設計
This design is for a 16-bit 1MSPS single-ended, multiplexed data acquisition system (DAQ) for dc inputs. The system is composed of a 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC), SAR ADC driver, reference driver, and multiplexer. The design shows the process to (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| SSOP (DB) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| TVSOP (DGV) | 14 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點