SN74LV8T596-Q1

現行

車用八位元電壓轉換移位暫存器

產品詳細資料

Operating temperature range (°C) -40 to 125 Rating Automotive
Operating temperature range (°C) -40 to 125 Rating Automotive
TSSOP (PW) 16 32 mm² 5 x 6.4 WQFN (BQB) 16 8.75 mm² 3.5 x 2.5
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package

  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67Mbps operation, (RPU = 1kΩ,CL = 30pF)
    • Up translation from 1.2V to 5V with 1.8V supply
    • Down translation from 5V to 0.8V or even less with any valid supply
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package

  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67Mbps operation, (RPU = 1kΩ,CL = 30pF)
    • Up translation from 1.2V to 5V with 1.8V supply
    • Down translation from 5V to 0.8V or even less with any valid supply
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17

The SN74LV8T596-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high impedance state. The operation of the OE input does not impact the internal register data

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The SN74LV8T596-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high impedance state. The operation of the OE input does not impact the internal register data

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

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* Data sheet SN74LV8T596-Q1 Automotive 8-bit Serial-Load Shift Register with Open-Drain Output and Logic-Level Shifter datasheet PDF | HTML 2024年 3月 22日

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TSSOP (PW) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian

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