SN74LVC1G80-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
- ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Supports Down Translation to VCC
- Maximum tpd of 6 ns at 3.3 V
- Low Power Consumption, 10-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff supports Partial-Power-Down Mode and Back-Drive Protection
The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
技術文件
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOT-SC70 (DCK) | 5 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點