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邏輯和電壓轉換
電壓轉換器及電平移位器
方向控制電壓轉換器

SN74LVC1T45

現行

具有可配置電平移位變化和 3 態輸出的單一位元雙電源供電匯流排收發器

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產品規格表

SN74LVC1T45

現行
產品規格表 立即訂購

產品詳細資料

Technology family LVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 300 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVC Applications GPIO Bits (#) 1 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 300 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 6 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DPK) 6 2.56 mm² 1.6 x 1.6
  • ESD protection exceeds JESD 22:
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.65V to 5.5V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4µA maximum ICC
  • ±24mA output drive at 3.3V
  • Ioff supports partial-power-down mode operation
  • Maximum data rates
    • 420Mbps (3.3V to 5V translation)
    • 210Mbps (translate to 3.3V)
    • 140Mbps (translate to 2.5V)
    • 75Mbps (translate to 1.8V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.65V to 5.5V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4µA maximum ICC
  • ±24mA output drive at 3.3V
  • Ioff supports partial-power-down mode operation
  • Maximum data rates
    • 420Mbps (3.3V to 5V translation)
    • 210Mbps (translate to 3.3V)
    • 140Mbps (translate to 2.5V)
    • 75Mbps (translate to 1.8V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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類型 標題 日期
* Data sheet SN74LVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. N) PDF | HTML 2024年 6月 24日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 2024年 5月 14日
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024年 4月 30日
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 2021年 7月 30日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003年 11月 6日
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note LVC Characterization Information 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

設計與開發

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使用指南: PDF | HTML
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模擬型號

HSPICE MODEL OF SN74LVC1T45

SCEJ231.ZIP (94 KB) - HSpice Model
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模擬型號

SN74LVC1T45 IBIS Model (Rev. C)

SCEM401C.ZIP (99 KB) - IBIS Model
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模擬型號

SN74LVC1T45 TINA-TI Reference Design (Rev. A)

SCEM545A.TSC (23812 KB) - TINA-TI Reference Design
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模擬型號

SN74LVC1T45 TINA-TI Spice Model (Rev. A)

SCEM546A.ZIP (7 KB) - TINA-TI Spice Model
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參考設計

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Design guide: PDF
電路圖: PDF
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電路圖: PDF
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電路圖: PDF
參考設計

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Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
DSBGA (YZP) 6 Ultra Librarian
SOT-23 (DBV) 6 Ultra Librarian
SOT-5X3 (DRL) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
USON (DPK) 6 Ultra Librarian
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