產品詳細資料

Configuration 1:1 SPST Number of channels 2 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 7.5 CON (typ) (pF) 14 ON-state leakage current (max) (µA) 2 Supply current (typ) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 50 Rating Automotive Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 2 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 7.5 CON (typ) (pF) 14 ON-state leakage current (max) (µA) 2 Supply current (typ) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 50 Rating Automotive Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Functional safety-capable
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C3B
  • 1.65 V to 5.5 V VCC operation
  • Inputs accept voltages to 5.5 V
  • High on-off output voltage ratio
  • High degree of linearity
  • High speed, typically 0.5 ns (VCC = 3 V, CL = 50 pF)
  • Rail-to-rail input output
  • Low on-state resistance, typically ≉6 Ω (VCC = 4.5 V)
  • Functional safety-capable
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C3B
  • 1.65 V to 5.5 V VCC operation
  • Inputs accept voltages to 5.5 V
  • High on-off output voltage ratio
  • High degree of linearity
  • High speed, typically 0.5 ns (VCC = 3 V, CL = 50 pF)
  • Rail-to-rail input output
  • Low on-state resistance, typically ≉6 Ω (VCC = 4.5 V)

The design of this dual bilateral analog switch is for 1.65 V to 5.5 V VCC operation. The SN74LVC2G66-Q1 can handle both analog and digital signals. The device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction. Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

The design of this dual bilateral analog switch is for 1.65 V to 5.5 V VCC operation. The SN74LVC2G66-Q1 can handle both analog and digital signals. The device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction. Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

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類型 標題 日期
* Data sheet SN74LVC2G66-Q1 Automotive Dual Bilateral Analog Switch datasheet (Rev. B) PDF | HTML 2021年 10月 27日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Functional safety information SN74LVC2G66-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FM PDF | HTML 2021年 10月 15日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
More literature Automotive Logic Devices Brochure 2014年 8月 27日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003年 11月 6日
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note LVC Characterization Information 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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DIP-ADAPTER-EVM — DIP 轉接器評估模組

Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.

The (...)

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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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模擬型號

SN74LVC2G66-Q1 PSpice Model (Rev. B)

SCEM562B.ZIP (27 KB) - PSpice Model
模擬型號

SN74LVC2G66-Q1 TINA-TI Reference Design (Rev. A)

SCEM573A.TSC (289 KB) - TINA-TI Reference Design
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SN74LVC2G66-Q1 TINA-TI Spice Model (Rev. A)

SCEM572A.ZIP (3 KB) - TINA-TI Spice Model
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VSSOP (DCU) 8 Ultra Librarian

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