首頁 邏輯和電壓轉換 電壓轉換器及電平移位器 方向控制電壓轉換器
首頁
邏輯和電壓轉換
電壓轉換器及電平移位器
方向控制電壓轉換器

SN74LVC8T245

現行

具有可配置電平移位變化和三態輸出的 8 位元雙電源供電匯流排收發器

立即訂購
產品規格表

SN74LVC8T245

現行
產品規格表 立即訂購

產品詳細資料

Technology family LVC Applications GPIO Bits (#) 8 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 25 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVC Applications GPIO Bits (#) 8 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 25 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SOP (NS) 24 117 mm² 15 x 7.8 SSOP (DB) 24 63.96 mm² 8.2 x 7.8 SSOP (DBQ) 24 51.9 mm² 8.65 x 6 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 TVSOP (DGV) 24 32 mm² 5 x 6.4 VQFN (RHL) 24 19.25 mm² 5.5 x 3.5
  • Control inputs V IH/V IL levels are referenced to V CCA voltage
  • V CC isolation feature – if either V CC input is at GND, all are in the high-impedance state
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 100-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control inputs V IH/V IL levels are referenced to V CCA voltage
  • V CC isolation feature – if either V CC input is at GND, all are in the high-impedance state
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 100-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74LVC8T245 is an eight bit non-inverting bus transceiver with configurable dual power supply rails that enables bidirectional voltage level translation. The SN74LVC8T245 is optimized to operate with V CCA and V CCB set at 1.65 V to 5.5 V. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V CCB. V CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The V CC isolation feature ensures that if either V CC input is at GND, all outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by V CCA.

The SN74LVC8T245 is an eight bit non-inverting bus transceiver with configurable dual power supply rails that enables bidirectional voltage level translation. The SN74LVC8T245 is optimized to operate with V CCA and V CCB set at 1.65 V to 5.5 V. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V CCB. V CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The V CC isolation feature ensures that if either V CC input is at GND, all outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by V CCA.
filter 尋找其它 方向控制電壓轉換器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 34
類型 標題 日期
* Data sheet SN74LVC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. C) PDF | HTML 2022年 12月 15日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
EVM User's guide TXV010xEVM Evaluation Module User's Guide PDF | HTML 2024年 2月 5日
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 2021年 7月 30日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Designing with SN74LVCXT245 and SN74LVCHXT245 Family of Direction Controlled 2015年 10月 27日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003年 11月 6日
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note LVC Characterization Information 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
開發板

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

使用指南: PDF | HTML
TI.com 無法提供
開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

使用指南: PDF
TI.com 無法提供
開發板

TXV0106-EVM — TXV0106 評估模組

TXV0106 評估模組 (EVM) 是一個易於使用的平台，用於評估 TXV0106 產品的功能與性能。此 EVM 具有選用電路和跨接器，可針對不同應用來配置產品。此產品提供固定與方向控制低偏斜、低抖動電壓轉換的選項。輸出可透過專屬的輸出啟用 (OE) 控制功能來啟用及停用。
使用指南: PDF | HTML
TI.com 無法提供
開發板

TXV0108-EVM — TXV0108 評估模組

TXV0108 評估模組 (EVM) 是一個易於使用的平台，用於評估 TXV0108 產品的功能與性能。此 EVM 具有選用電路和跨接器，可針對不同應用來配置產品。此產品提供固定與方向控制低偏斜、低抖動電壓轉換的選項。輸出可透過專屬的輸出啟用 (OE) 控制功能來啟用及停用。
使用指南: PDF | HTML
TI.com 無法提供
模擬型號

SN74LVC8T245 IBIS Model

SCEM494.ZIP (56 KB) - IBIS Model
下載
參考設計

TIDEP0025 — 適用於工業通訊和馬達控制的單晶片驅動

This reference design implements hardware interface based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows you to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designs with a low (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0022 — 具有整合式 BiSS C 主介面的 ARM MPU 參考設計

Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0035 — 具有整合式 HIPERFACE DSL 主介面的 ARM MPU 參考設計

This reference design implements HIPERFACE DSL master protocol on Industrial Communication Sub-System (PRU-ICSS). The two-wire interface allows integration of position feedback wires into motor cable.  It consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0050 — EnDat 2.2 系統參考設計

This reference design implements EnDat 2.2 Master protocol stack and hardware interface based on HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of EnDat 2.2 Master protocol stack, half-duplex communications using RS-485 transceivers and the line termination (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0057 — 基於 PRU-ICSS 並採用 AM437x 的多協定數位位置編碼器主介面參考設計

This is a reference design for industrial communication on Sitara™ processors with programmable real-time unit and industrial communication subsystem (PRU-ICSS). This design describes the integrated multi-protocol digital position encoder master interface support. The supported digital (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0046 — 基於 AM57x 使用 OpenCL 進行 DSP 加速的 Monte-Carlo 模擬參考設計

TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0047 — 採用 TI AM57x 處理器參考設計的電源和熱能設計考量

This is a reference design based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037.  It includes (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (DW) 24 Ultra Librarian
SOP (NS) 24 Ultra Librarian
SSOP (DB) 24 Ultra Librarian
SSOP (DBQ) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
TVSOP (DGV) 24 Ultra Librarian
VQFN (RHL) 24 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片