封裝資訊
| 封裝 | 針腳 TSSOP (PW) | 16 |
| 操作溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送業者 90 | TUBE |
TLC2554 的特色
- Maximum Throughput 400 KSPS
- Built-In Reference and 8× FIFO
- Differential/Integral Nonlinearity Error:
±1 LSB - Signal-to-Noise and Distortion Ratio:
69 dB, fi = 12 kHz - Spurious Free Dynamic Range: 75 dB,
fi = 12 kHz - SPI/DSP-Compatible Serial Interfaces With SCLK up to 20 MHz
- Single Supply 5 Vdc
- Analog Input Range 0 V to Supply Voltage With 500 kHz BW
- Hardware Controlled and Programmable Sampling Period
- Low Operating Current (4 mA at 5.5 V External Ref, 6 mA at 5.5 V, Internal Ref)
- Power Down: Software/Hardware Power-Down Mode (1 uA Max, Ext Ref),
Auto Power-Down Mode (1 uA, Ext Ref) - Programmable Auto-Channel Sweep
TLC2554 的說明
The TLC2558 and TLC2554 are a family of high-performance, 12-bit low power, 1.6 us, CMOS analog-to-digital converters (ADC) which operate from a single 5 V power supply. These devices have three digital inputs and a 3-state output [chip select (CS\), serial input-output clock (SCLK), serial data input (SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the start of a serial data frame.
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special pin, CSTART\, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular among high-performance signal processors. The TLC2558 and TLC2554 are designed to operate with very low power consumption. The power-saving feature is further enhanced with software/hardware/auto power down modes and programmable conversion speeds. The converter uses the external SCLK as the source of the conversion clock to achieve higher (up to 1.6 us when a 20 MHz SCLK is used) conversion speed. There is a 4-V internal reference available. An optional external reference can also be used to achieve maximum flexibility.