It is best to route traces on the PCB from the ESD Source to the TVS without switching layers by VIA. Figure 2-5 shows two examples. In Case 1, there is no VIA between the ESD Source and the TVS, so that I_ESD is forced to the TVS protection pin before the VIA in the path to the Protected IC. In this case the VIA represents L₄ shown in Figure 2-1. In Case 2, I_ESD branches between the Protected IC and the VIA to the TVS protection pin. In this case the VIA represents L₂ in Figure 2-1. This practice should be avoided. The inductance of the VIA is between the TVS and the path from the ESD Source to the Protected IC. This has two detrimental effects: Since current seeks the path to ground with the least impedance, the Protected IC may take the brunt of the current in I_ESD and any current that does pass through the VIA will increase the voltage presented to the Protected IC by L_VIA(dI_ESD/dt).

There may be cases where the designer has no choice but to place the TVS on a different layer than the ESD Source. Figure 2-6 shows Case 3 , a variation to Case 2. In Case 3, I_ESD is forced to the protection pin of the TVS before I_ESD has a path to the Protected IC. This is an acceptable compromise to Case 2.

These three cases represent examples when VIAs are used between the ESD Source and the Protected IC. It is best to avoid this practice, but if necessary Case 1 is the preferred method, Case 2 should be avoided, and Case 3 is acceptable if there is no alternative.

Summary

• Avoid VIAs between the ESD Source and TVS if possible
• If a VIA is required between the ESD Source and the Protected IC, route directly from the ESD Source to the TVS before using the VIA