SLVA680A February   2015  – April 2022 ESD401 , TPD12S015 , TPD12S015A , TPD12S016 , TPD12S520 , TPD12S521 , TPD13S523 , TPD1E05U06 , TPD1E10B06 , TPD1E10B09 , TPD1S414 , TPD1S514 , TPD2E001 , TPD2E001-Q1 , TPD2E009 , TPD2E1B06 , TPD2E2U06-Q1 , TPD2EUSB30 , TPD2S017 , TPD3S014 , TPD3S044 , TPD4E001-Q1 , TPD4E004 , TPD4E02B04 , TPD4E05U06 , TPD4E05U06-Q1 , TPD4E101 , TPD4E1U06 , TPD4E6B06 , TPD4EUSB30 , TPD4S010 , TPD4S014 , TPD4S1394 , TPD4S214 , TPD5S115 , TPD5S116 , TPD6E004 , TPD6E05U06 , TPD6F002-Q1 , TPD6F003 , TPD6F202 , TPD7S019 , TPD8E003 , TPD8F003

 

  1.   Trademarks
  2. 1Introduction
  3. 2PCB Layout Guidelines for Optimizing Dissipation of ESD
    1. 2.1 Optimizing Impedance for Dissipating ESD
    2. 2.2 Limiting EMI from ESD
    3. 2.3 Routing with VIAs
    4. 2.4 Optimizing Ground Schemes for ESD
  4. 3Conclusion
  5. 4Revision History

Conclusion

Designing ESD protection into a system can be successful with the proper techniques applied. Following these ESD layout guide outlines will ensure the TVS has optimum conditions for dissipating the ESD.

In summary:

  • Control Impedances around the TVS for dissipating ESD current, IESD:
    • Minimize any inductance between the ESD Source and the path to ground through the TVS
    • Place the TVS as near to the connector as design rules allow
    • Place the Protected IC much further from the TVS than the TVS is to the connector
    • Do not use stubs between the TVS and the Protected Line, route directly from the ESD Source to the TVS
    • Minimizing inductance between the TVS and ground is critical
  • Limit the effects of EMI on unprotected circuits:
    • Do not route unprotected circuits in the area between the ESD Source and the TVS
    • Place the TVS as near to the connector as design rules allow
    • Route with straight traces between the ESD Source and the TVS if possible
    • If corners must be used curves are preferred and a maximum of 45° is acceptable
  • Properly use VIAs to maximize ESD dissipation by the TVS:
    • Avoid VIAs between the ESD Source and the TVS if possible
    • If a VIA is required between the ESD Source and the Protected IC, route directly from the ESD Source to the TVS before using the VIA
  • Use a grounding scheme that has very low impedance:
    • Connect the TVS Ground Pin directly to a same layer ground plane that has nearby VIAs stitching to an adjacent internal ground plane
    • Use multiple ground planes when possible
    • Use a chassis screw, connected to PCB ground, near to the TVS and ESD Source (for example, the connector ground shield)
    • Use VIAs of large diameter with a large drill, which lowers impedance

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