SLVAF66 June   2021 DRV3255-Q1 , DRV8300 , DRV8301 , DRV8302 , DRV8303 , DRV8304 , DRV8305 , DRV8305-Q1 , DRV8306 , DRV8307 , DRV8308 , DRV8320 , DRV8320R , DRV8323 , DRV8323R , DRV8340-Q1 , DRV8343-Q1 , DRV8350 , DRV8350F , DRV8350R , DRV8353 , DRV8353F , DRV8353R

 

  1. 1 Introduction to High-Power Motor Applications
    1. 1.1 Effects of a Poorly-Designed High-Power Motor Driver System
    2. 1.2 Example of the High-Power Design Process
  2. 2 Examining a High-Power Motor Drive System at a High Level
    1. 2.1 Anatomy of the Motor Drive Power Stage and How to Troubleshoot
    2. 2.2 Troubleshooting a High-Power System
  3. 3 High-Power Design Through MOSFETs and MOSFET Gate Current (IDRIVE)
    1. 3.1 MOSFET Gate Current
      1. 3.1.1 How Gate Current Causes Damage
      2. 3.1.2 Gate Resistors and Smart Gate Drive Technology
        1. 3.1.2.1 Gate Resistors
        2. 3.1.2.2 Smart Gate Drive and Internally-Controlled Sink and Source Gate Currents
        3. 3.1.2.3 Summary for Gate Resistors and Smart Gate Drive Technology
      3. 3.1.3 Example Gate Current Calculation for a Given FET
  4. 4 High-Power Design Through External Components
    1. 4.1 Bulk and Decoupling Capacitors
      1. 4.1.1 Note on Capacitor Voltage Ratings
    2. 4.2 RC Snubber Circuits
    3. 4.3 High-Side Drain to Low-Side Source Capacitor
    4. 4.4 Gate-to-GND Diodes
  5. 5 High-Power Design Through a Parallel MOSFET Power Stage
  6. 6 High-Power Design Through Protection
    1. 6.1 VDS and VGS Monitoring
      1. 6.1.1 Turning Off the FETs During an Overcurrent, Shoot-Through, or FET Shorting Event
    2. 6.2 Passive Gate-to-Source Pulldown Resistors
    3. 6.3 Power Supply Reverse Polarity or Power Supply Cutoff Protection
  7. 7 High-Power Design Through Motor Control Methods
    1. 7.1 Brake versus Coast
      1. 7.1.1 Algorithm-Based Solutions
      2. 7.1.2 External Circuit Solutions
      3. 7.1.3 Summary of Brake versus Coast
  8. 8 High-Power Design Through Layout
    1. 8.1 What is a Kelvin Connection?
    2. 8.2 General Layout Advice
  9. 9 Conclusion
  10. 10Acknowledgments

6.1 VDS and VGS Monitoring

Figure 6-1 Example Implementation of VDS and VGS Monitors

As the names imply, VDS and VGS monitoring simply aim to monitor the voltage at the gate, source, and drain of the FET.

In a shoot-through example, a high-side FET within one phase, or inverter leg, is turned on. After some time, the input signals are changed to turn off the high-side FET and then turn on the low-side FET within the same phase. If the high-side FET and the low-side FET are turned on at the same time, the motor is bypassed and current flows through the much lower resistance path of the high-side and low-side FET at the same time.

The problem with a shoot-through event is that the resistive path to ground is really low. For example, the resistive path from a 48-V supply through the motor resistance (between hundreds of milliohms and one ohm) is much higher resistance than when the supply is shorted to ground through the ones of milliohms resistance of the FETs. The excess current can exceed the current rating of the FETs, can cause massive inductive spiking which can violate the absolute maximum ratings of the device, and can also cause the PCB to increase dramatically in temperature which can result in permanent damage to the PCB.

If the difference between the gate and source voltage (VGS) is monitored, we can understand whether or not the FET is on and conducting current. If the difference between the drain and source voltage is monitored, we can understand if the current is conducting through the FET. As a result, we can monitor these two voltages and make intelligent decisions when to turn the FETs on and off and prevent the driver from turning on both FETs in the same phase. In short, VGS monitors determine if the gate is on and VDS monitors determine if current is flowing when the gate is on.

The typical implementation is to monitor these voltages with comparators. Some integrated devices have some shoot-through protection features by inserting a time delay between turning off one FET and turning on the other, or not allowing the input signals to turn the high and low side on at the same time. However, some devices do not integrate the VGS or VDS monitors within the device, and will therefore, not override the inputs in the case of a shoot-through event. It is always best to check the data sheet of the gate driver for more information.

In the case of TI technology, Smart Gate Drive relies on the states of the VGS and VDS monitors to determine whether to allow or prevent the gates from turning on. More information is found in the Understanding Smart Gate Drive application note.

In summary:

  • Monitoring VGS determines if the FET is on
  • Monitoring VDS determines if current is flowing through the FET when the gate is on
  • Including VGS and VDS comparator outputs into the commutation logic, which overrides the inputs, protects the system during high current or damaging power stage situations such as shoot-through