When PCBs are manufactured, physics dictates that some more resistors, inductors, and capacitors are added to the system. These added components are the result of parasitics - an example is illustrated in Figure 8-2.

One of the primary goals of layout is to minimize these parasitics so they are effectively negligible. What makes high power design difficult is that more current and voltage makes the effects of these parasitics more pronounced.

As a result, an entire application note has been devoted to Best Practices for Board Layout of Motor Drivers. It is highly recommended to read through the document in its entirety.

However, additional bullet points have been added here to help in the context of the high-power gate driver devices offered by TI:

• Actual PCBAs have parasitic components that are added to the system

  • Long traces add capacitance and resistance
  • Thin traces also add resistance and inductance

• 10 mil/A with 1-oz copper pour is a guideline for the trace width but it also applies to vias, specifically angular ring area. The larger or wider the traces and vias are, the less inductance.

  • As such, use at least 15 mil gate current source and sink paths, but 20 mil is preferred
    Note: The 10 mil/A with 1-oz copper guideline starts to break and wider traces are required as a result of heat within the middle layers
• To get better thermal and current capability it is recommended to provide the VDC, motor phases, and GND power polygons in the external layers and, if possible, repeat the polygons in internal layers as well
• Making sections of a trace thinner and smaller in the same trace adds impedance mismatch
  • Use teardrops or planes to smooth out the mismatch
• More current means higher voltage spiking due to the parasitic effects
• Component footprints, in addition to the components, add parasitics
• Vias in the path add parasitics, namely inductance
• The return path must be understood:
  • DC current spreads out on the GND planes as far as it can go, whereas high-frequency current gravitates underneath the corresponding high-speed trace. This is why common GND, as opposed to split GND, is always better unless current needs to be diverted from flowing in a certain area of the board.
• Common ground is always better than split GND from a parasitic perspective. Split GND is only ever used to divert high-frequency current as well as large amounts of current away from the sensitive components. That means that these signals must be traveling towards or near those components to warrant a split GND.
  • If a split GND is chosen, then know inductance is added to some paths
• For additional understanding, imagine that you are the current: draw the loop from the source of the pin or component to the GND pin of the device or external connector. Make the loop as small as possible. This sometimes means adding lots of vias in the planes, increasing ground plane coverage, or rearranging components.
• Experience shows that the price difference between 100 and 300 GND stitching vias is negligible in PCB manufacturing. Create a plane of GND stitching vias to connect outer- and inner-layer GNDs.
  • Manually place GND stitching vias where the automated tools fail
• The most important signals and component locations on a typical gate driver IC are included in the following list, in descending order of importance:

1. Voltage regulators and their associated capacitors (like VCP, VGLS, or low-voltage regulators AVDD, DVDD, and so forth) (most critical)
2. Bypass capacitors for input supplies and reference voltages (like VM, GND, and CSAREF)
3. Signal path and higher current or power paths (like GHx, GLx, and SHx)
4. Digital signals that switch often, ordered by frequency (like SPI or PWM signals)
5. Digital signals that do not switch often (like ENABLE or nFAULT) (least critical)