Dean Banerjee
Have you ever been frustrated just trying to get your phase-locked loop (PLL) to lock? Premature assumptions can make the debugging process much longer and more tedious than necessary. By following the processes outlined here for verifying communication and establishing lock, the debugging process can be simplified.
The first step is to verify the PLL’s ability to respond to programming. If the PLL is not locking and you cannot read back from it, try sending software commands that require a minimum amount of hardware commands to work. One possibility is to power the PLL up and down via software (not pin) and look for a predictable current change or bias-voltage-level change on a pin. Many PLLs have a bias level on their input (OSCin) pin that is Vcc/2 when powered up and 0V when powered down.
If the PLL has integrated voltage controlled oscillators (VCOs), look at the low-dropout (LDO) output pin voltages and see if they react to power-down and power-up commands. It might be possible to toggle input/output (I/O) pins such as the MUXout pin on many LMX PLLs. If you can verify communications with these methods, then go ahead and try to achieve lock.
If you cannot verify communication, then look for common culprits such as the following:
Once you have verified communication, the next step is to try to achieve lock with the PLL. These are some of the more common reasons for an unlocked PLL:
The debugging process for getting a PLL to lock can be much simpler by following a systematic approach and not making premature assumptions. Figure 1 shows a flowchart that can be used to guide one through this process.
If you would like to learn more about the challenges of unlocked PLLs, check out the Texas Instruments portfolio of phase lock loops.
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