Gehäuseinformationen
| Gehäuse | Pins HTSSOP (DDW) | 44 |
| Betriebstemperaturbereich (°C) 0 to 70 |
| Gehäusemenge | Träger 35 | TUBE |
Merkmale von TPA3250
- Differential Analog Inputs
- Total Output Power at 10%THD+N
- 70-W Stereo Continuous into 8 Ω in BTL
Configuration at 32 V - 130-W Stereo Peak into 4 Ω in BTL
Configuration at 32 V
- 70-W Stereo Continuous into 8 Ω in BTL
- Total Output Power at 1%THD+N
- 60-W Stereo Continuous into 8 Ω in BTL
Configuration at 32 V - 105-W Stereo Peak into 4 Ω in BTL
Configuration at 32 V
- 60-W Stereo Continuous into 8 Ω in BTL
- Advanced Integrated Feedback Design with High-
speed Gate Driver Error Correction
(PurePath™ Ultra-HD)- Signal Bandwidth up to 100 kHz for High
Frequency Content From HD Sources - Ultra Low 0.005% THD+N at 1 W into 4 Ω
and <0.01% THD+N to Clipping - 60 dB PSRR (BTL, No Input Signal)
- <60 µV (A-Weighted) Output Noise
- >110 dB (A Weighted) SNR
- Signal Bandwidth up to 100 kHz for High
- Multiple Configurations Possible:
- Stereo, Mono, 2.1 and 4xSE
- Click and Pop Free Startup and Stop
- 92% Efficient Class-D Operation (8 Ω)
- Wide 12-V to 36-V Supply Voltage Operation
- Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short Circuit
Protection) With Error Reporting - EMI Compliant When Used With Recommended
System Design
Beschreibung von TPA3250
The TPA3250 device is a high performance class-D power amplifier that enables true premium sound quality with class-D efficiency. It features an advanced integrated feedback design and proprietary high-speed gate driver error correction (PurePath™ Ultra-HD). This technology allows ultra low distortion across the audio band and superior audio quality. With a 32V power supply the device can drive up to 2 × 130 W peak into 4-Ω load and 2 × 70 W continuous into 8-Ω load and features a 2 VRMS analog input interface that works seamlessly with high performance DACs such as TI’s PCM5242. In addition to excellent audio performance, TPA3250 achieves both high power efficiency and very low power stage idle losses below 1 W. This is achieved through the use of 60 mΩ MOSFETs and an optimized gate driver scheme that achieves significantly lower idle losses than typical discrete implementations.