Información de empaque
| Encapsulado | Pines VQFN (RSH) | 56 |
| Rango de temperatura de funcionamiento (℃) -40 to 150 |
| Cant. de paquetes | Empresa de transporte 3,000 | JEDEC TRAY (10+1) |
Características para TMS320F28P550SJ
- Real-time processing:
- 150MHz C28x 32-bit DSP CPU
- Equivalent to 300MHz Arm® Cortex®-M7 based device on real-time signal chain performance (see the Real-time Benchmarks Showcasing C2000™ Control MCU’s Optimized Signal Chain Application Note
- IEEE 754 single-precision Floating-Point Unit (FPU32)
- Trigonometric Math Unit
(TMU)
- Support for Nonlinear Proportional Integral Derivative (NLPID) control
- CRC Engine and Instructions (VCRC)
- Programmable Control Law Accelerator (CLA)
- 150MHz
- Equivalent to 200MHz Arm® Cortex®-M7 based device on real-time signal chain performance (see the Real-time Benchmarks Showcasing C2000™ Control MCU’s Optimized Signal Chain Application Note
- IEEE 754 single-precision floating-point instructions
- Executes code independently of main CPU
- On-chip memory
- 1088KB of flash (ECC-protected) across five
independent banks
- Four 256KB banks
- One 64KB bank, ideal of LFU/Bootloaders/data
- 8KB of OTP (One Time Programmable flash memory)
- 133KB of RAM (ECC/Parity protected)
- 1088KB of flash (ECC-protected) across five
independent banks
- Security
- Secure Boot
- JTAG Lock
- Advanced Encryption Standard (AES) accelerator
- Unique Identification (UID) number
- Clock and system control
- Two internal 10MHz oscillators
- Crystal oscillator or external clock input
- Windowed watchdog timer module
- Missing clock detection circuitry
- Dual-clock Comparator (DCC)
- 3.3V I/O design
- Internal VREG generation allows for single-supply design
- Brownout reset (BOR) circuit
- 5V failsafe and tolerant capability on 4 GPIOs for PMBUS/I2C support
- Configurable 1.35V VIH on 4 GPIOs
- System peripherals
- 6-channel Direct Memory Access (DMA) controller
- 91 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins (22 shared with Analog)
- 17 digital inputs on analog pins
- Enhanced Peripheral Interrupt Expansion (ePIE)
- Multiple low-power mode (LPM) support
- Communications peripherals
- One Power-Management Bus (PMBus) interface
- Fast Plus Mode Support - 1MHz SCL
- 5V/3.3V/1.35V VIH support on select pins
- Two Inter-integrated Circuit (I2C) interfaces
- Two Controller Area Network with Flexible Data-Rate (CAN FD/MCAN) bus port
- 4KB message RAM per MCAN module, independent of system memory
- Ability to re-use RAM for CPU data variables if MCAN is not used
- One Universal Serial Bus (USB 2.0 MAC + PHY)
- Two Serial Peripheral Interface (SPI) ports
- Three UART-compatible Serial Communication Interface (SCI)
- One UART-compatible Local Interconnect Network (LIN) interface
- Fast Serial Interface (FSI) with one transmitter and one receiver (up to 200Mbps)
- One Power-Management Bus (PMBus) interface
- Analog system
- Five 3.9MSPS, 12-bit Analog-to-Digital Converters
(ADCs)
- Up to 39 external channels (includes one gpdac output)
- Four integrated Post-Processing Blocks (PPB) per ADC
- Four windowed comparators (CMPSS) with 12-bit reference Digital-to-Analog Converters (DACs)
- Digital glitch filters
- Low DAC output to pin capability on CMPSS1
- One 12-bit buffered DAC output
- Three Programmable
Gain Amplifiers (PGAs)
- Unity gain support
- Inverting and non-inverting gain mode support
- Programmable output filtering
- Five 3.9MSPS, 12-bit Analog-to-Digital Converters
(ADCs)
- Enhanced control peripherals
- 24 ePWM channels with 12
channels that have high-resolution capability (150ps resolution)
- Integrated dead-band support
- Integrated hardware trip zones (TZs)
- Two Enhanced Capture (eCAP) modules
- Three Enhanced Quadrature Encoder Pulse (eQEP) modules with support for CW/CCW operation modes
- Embedded Pattern Generator (EPG)
- 24 ePWM channels with 12
channels that have high-resolution capability (150ps resolution)
- Configurable Logic Block (CLB)
- 2 tiles
- Augments existing peripheral capability
- Supports position manager solutions
- Neural-network Processing Unit (NPU)
- Highly Optimized for Deep Convolutional Neural Networks (CNN)
- Variable weights and data lengths
- 8-bit and 4-bit weights
- 8-bit and 4-bit data
- 600MOPS (Mega Operations Per Second) at 75MHz on 8bWx8bD
- 1200MOPS at 75MHz on 4bWx8bD
- Up to 10x NN inferencing performance improvement vs SW techniques
- No direct coding required, TI AI tools generate FW libraries
- Real-time control focused
Edge AI Models
- ARC fault example
- Motor fault example
- Live Firmware Update (LFU)
- Diagnostic features
- Memory Power-On Self-Test (MPOST)
-
Functional Safety-Compliant targeted
- Developed for functional safety applications
- Documentation available to aid ISO 26262 and IEC 61508 system design
- Systematic capability up to ASIL D and SIL 3 targeted
- Hardware integrity up to ASIL B targeted
- Safety-related certification
- ISO 26262 certification up to ASIL B by TÜV SÜD planned
- Package options:
- 128-pin Thin Quad Flatpack (TQFP)[PDT suffix]
- 100-pin Low-profile Quad Flatpack (LQFP)[PZ suffix]
- 80-pin TQFP [PNA suffix]
- 64-pin LQFP [PM suffix]
- 56-pin Very Thin Quad Flatpack No-Lead (VQFN) [RSH suffix]
- Temperature options:
- Junction (TJ): –40°C to 150°C
Descripción de TMS320F28P550SJ
The TMS320F28P55x (F28P55x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
- Motor drives
- Appliances
- Hybrid, electric & powertrain systems
- Solar & EV charging
- Digital power
- Body electronics & lighting
- Test & measurement
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 150MHz of signal-processing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The C28x CPU is further boosted by the Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and VCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent 32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own dedicated memory resources and it can directly access the key peripherals that are required in a typical control system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware task-switching.
The Neural-network Processing Unit (NPU) can support machine-learning inferencing using pre-trained models. Capable of 600–1200MOPS (Mega Operations Per Second) with model support for ARC fault detection or Motor Fault detection, the NPU provides up to 10x NN inferencing cycle improvement versus a SW-only-based implementation. Load and train models with the Model Composer GUI from TI or with the Tiny ML Modelmaker for an advanced set of capabilities. Source code for the C28x is generated by these tools, no manual coding is necessary. For customers who rely on their own AI training framework, TI’s Neural Network Compiler can help port your AI model to be compatible with many C28x-based MCUs. For those interested in reference solutions, request access to TI’s Arc Fault Detection Project or the Motor Bearing Fault Detection Project.
The F28P55x supports up to 1088KB of flash memory divided into four 256KB banks plus one 64KB bank, which enable programming one bank and execution in another bank in parallel. Up to 133KB of on-chip SRAM is also available to supplement the flash memory.
The Live Firmware Update hardware enhancements on F28P55x allow fast context switching from the old firmware to the new firmware to minimize application downtime when updating the device firmware.
High-performance analog blocks are integrated on the F28P55x real-time microcontroller (MCU) and are closely coupled with the processing and PWM units to provide optimal real-time signal chain performance. Twenty-four PWM channels, all supporting frequency-independent resolution modes, enable control of various power stages from a 3-phase inverter to power factor correction and advanced multilevel power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus, LIN, and CAN FD) and offers multiple pin-muxing options for optimal signal placement.
Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page.
The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered.
Ready to get started? Check out the TMDSCNCD28P55X evaluation board or the LAUNCHXL-F28P55X development kit, and download C2000Ware.