SN74AS109A
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
These devices contain two independent J-K\ positive-edge-triggered
flip-flops. A low level at the preset () or clear (
) inputs sets or resets the outputs
regardless of the levels of the other inputs. When
and
are inactive (high), data at the J
and K\ inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold-time
interval, data at the J and K\ inputs can be changed without
affecting the levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by grounding K\ and tying J high. They
also can perform as D-type flip-flops if J and K\ are tied together.
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.
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- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点