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SN74AS194

アクティブ

4 ビット双方向ユニバーサル・シフト・レジスタ

製品詳細

Configuration Universal Bits (#) 4 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 53000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Universal Bits (#) 4 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 53000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Parallel-to-Serial, Serial-to-Parallel Conversions
  • Left or Right Shifts
  • Parallel Synchronous Loading
  • Direct Overriding Clear
  • Temporary Data-Latching Capability
  • Package Options Include Plastic Small-Outline Packages (D), Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
  • Parallel-to-Serial, Serial-to-Parallel Conversions
  • Left or Right Shifts
  • Parallel Synchronous Loading
  • Direct Overriding Clear
  • Temporary Data-Latching Capability
  • Package Options Include Plastic Small-Outline Packages (D), Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:

  • Inhibit clock (temporary data latch/do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.

The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.

These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:

  • Inhibit clock (temporary data latch/do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.

The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート 4-Bit Bidirectional Universal Shift Registers データシート (Rev. A) 1994年 12月 1日

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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