74ACT11286
- Inputs Are TTL-Voltage Compatible
- Generates Either Odd or Even Parity for Nine Data Lines
- Cascadable for n-Bits Parity
- Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process - 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)
EPIC is a trademark of Texas Instruments Incorporated.
The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.
The 
control input
is implemented specifically to accommodate cascading. When the is low, the parity tree is
disabled and the PARITY ERROR output remains at a high logic level,
regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR
indicates a parity error when either an even number of inputs (A
through I) are high and PARITY I/O is forced to a low logic level, or
when an odd number of inputs are high and PARITY I/O is forced to a
high logic level.
The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.
The 74ACT11286 is characterized for operation from -40°C to 85°C.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | 9-Bit Parity Generator/Checker With Bus Driver Parity I/O Ports datasheet (Rev. B) | 1996/04/01 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치