The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) | PDF | HTML | 2019/02/21 |
| Application note | Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design | 2018/05/30 | ||
| EVM User's guide | ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) | 2018/01/09 |
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ADC08DJ3200 평가 모듈(EVM)을 통해 ADC08DJ3200 장치를 평가할 수 있습니다. ADC08DJ3200은 저전력, 8비트, 듀얼 채널 3.2 GSPS 또는 단일 채널 6.4 GSPS, RF 샘플링 아날로그-디지털 컨버터(ADC)로 버퍼링된 아날로그 입력을 지원하며, 프로그래밍 가능한 NCO(숫자 제어 오실레이터) 및 데시메이션 설정을 지원하며 JESD204B 인터페이스를 제공하는 통합 디지털 다운 컨버터입니다.
ADC08JD3200EVM에는 광범위한 신호 소스 및 주파수를 수용할 수 있는 변압기 결합 커플 아날로그 (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.