CD40117B
- One standard "B" output will drive eight terminator circuits.
- Will terminate a CMOS data bus with up to 40 B-series inputs inputs or 3-state outputs connected at VDD of 5 V.
- Input terminal protected by standard "B" series ESD protection network.
- Preserves final logic state.
- Output after switching is closer to VDD or VSS rail than with a resistor.
- Requires only one solder connection.
- Open circuited terminator not used will not affect performance.
- Can be connected to any CMOS I/O line.
- Draws current only when logic state is changing.
- Can be preset.
- Applications
- Error state identification.
- Replaces pull-up or pull-down resistors
- Avoids floating inputs in modular systems
- Sharpens transistors (hysteresis)
- Anti-bounce circuit
NOT RECOMMENDED FOR NEW DESIGNS
CD40117B is a dual 4-bit terminator that can be programmed by means of STROBE and DATA control bits to function as pull-up or pull-down resistors. The CD40117B can also be programmed to function as latches to terminate any open or unused CMOS logic when used with 3-state logic or during a power-down condition. Considerable savings in power and board space can be realized when this device is used to replace pull-up or pull-down resistors. When the STROBE is in the logic "1" state, the terminator functions as a pull-up resistor if the DATA input is a logic "1" or as a pull down resistor if the DATA input is a logic "0".
When the STROBE is in the logic "0" state, the terminator performs the latch functions, i.e., it follows the changing states of the bus. If the bus goes into the high-Z state or into a power-down condition, the latched terminator retains the data ("1" or "0") that the bus carried before it switched to the high-Z or power-down state. If and when the bus changes from the high-Z state to the state opposite to that which the latch is storing, the bus will override the latch and the terminator will reflect the state on the bus. The small geometries chosen for the inverters in the latch allow this override mode. When checking the data bus whose last state is being preserved by the terminator, a resistor should be used in series with the probe whose input capacitance could trip the small latches. The resistance should be in excess of the output impedance of the latch, i.e., R should be > 30 K
at VDD = 10 V.
The STROBE and DATA inputs in each section can be paralleled allowing this device to be used as an 8-bit bus terminator.
The CD40117B types are supplied in 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | CD40117B TYPES datasheet (Rev. C) | 2003/08/21 | |
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| User guide | Signal Switch Data Book (Rev. A) | 2003/11/14 | ||
| Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001/12/03 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| PDIP (N) | 14 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치