CD74HCT297

Name: CD74HCT297
Brand: TI
SKU: CD74HCT297
Price: 1.368 USD

활성

고속 CMOS 로직 디지털 위상 동기 루프

지금 주문

데이터 시트

document-pdfAcrobat CD54/74HC297, CD74HCT297 datasheet (Rev. B) (영어)

CD74HCT297

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

HCT

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

HCT

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

16

181.42 mm² 19.3 x 9.4

Digital Design Avoids Analog Compensation Errors
Easily Cascadable for Higher Order Loops
Useful Frequency Range
- K-Clock...DC to 55MHz (Typ)
- I/D-Clock...DC to 35MHz (Typ)
Dynamically Variable Bandwidth
Very Narrow Bandwidth Attainable
Power-On Reset
Output Capability
- Standard...XORPD_OUT, ECPD_OUT
- Bus Driver...I/D_OUT
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
’HC297 Types
- Operation Voltage...2 to 6V
- High Noise Immunity N_IL = 30%, N_IH = 30% of V_CC at 5V
CD74HCT297 Types
- Operation Voltage...4.5 to 5.5V
- Direct LSTTL Input Logic Compatibility V_IL =0.8V (Max), V_IH =2V (Min)
- CMOS Input Compatibility I_I 1µA at V_OL , V_OH

Data sheet acquired from Harris Semiconductor

Digital Design Avoids Analog Compensation Errors
Easily Cascadable for Higher Order Loops
Useful Frequency Range
- K-Clock...DC to 55MHz (Typ)
- I/D-Clock...DC to 35MHz (Typ)
Dynamically Variable Bandwidth
Very Narrow Bandwidth Attainable
Power-On Reset
Output Capability
- Standard...XORPD_OUT, ECPD_OUT
- Bus Driver...I/D_OUT
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
’HC297 Types
- Operation Voltage...2 to 6V
- High Noise Immunity N_IL = 30%, N_IH = 30% of V_CC at 5V
CD74HCT297 Types
- Operation Voltage...4.5 to 5.5V
- Direct LSTTL Input Logic Compatibility V_IL =0.8V (Max), V_IH =2V (Min)
- CMOS Input Compatibility I_I 1µA at V_OL , V_OH

Data sheet acquired from Harris Semiconductor

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).

These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.

The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.

The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by V_CC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).

These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.

The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.

The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by V_CC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.

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