SN54ACT8997
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Serial Test Bus
- Allow Partitioning of System Scan Paths
- Can Be Cascaded Horizontally or Vertically
- Select Up to Four Secondary Scan Paths to Be Included in a Primary Scan Path
- Include 8-Bit Programmable Binary Counter to Count or Initiate Interrupt Signals
- Include 4-Bit Identification Bus for Scan-Path Identification
- Inputs Are TTL Compatible
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process - Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
The 'ACT8997 are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components facilitates testing of complex circuit-board assemblies.
The 'ACT8997 enhance the scan capability of TI's SCOPETM family by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8997 for inclusion in the primary scan path. These devices also provide buffering of test signals to reduce the need for external logic.
By loading the proper values into the instruction register and data registers, the user can select up to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.
All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on either the rising or falling edge of DCI.
The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.
The SN54ACT8997 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8997 is characterized for operation from 0°C to 70°C.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled IEEE Std datasheet (Rev. D) | 1996/12/01 | |
| * | SMD | SN54ACT8997 SMD 5962-93239 | 2016/06/21 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021/07/26 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004/06/22 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997/06/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996/04/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| CDIP (JT) | 28 | Ultra Librarian |
| LCCC (FK) | 28 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치