홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 비인버팅 버퍼 및 드라이버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
비인버팅 버퍼 및 드라이버

SN54LVCH244A

활성

버스 홀드 및 3상 출력을 지원하는 군사용 8채널, 2V~3.6V 버퍼

지금 주문
데이터 시트

SN54LVCH244A

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.9 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.9 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.

These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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기술 자료

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28개 모두 보기
유형 직함 날짜
* Data sheet SN54LVCH244A, SN74LVCH244A datasheet (Rev. O) 2007/02/05
* SMD SN54LVCH244A SMD 5962-97542 2016/06/21
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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