SN74ABT16825

활성

TTL 호환 CMOS 입력 및 3상 출력을 지원하는 18채널 4.5V~5.5V 버퍼

제품 상세 정보

Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 Supply current (max) (µA) 32000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 Supply current (max) (µA) 32000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Members of Texas Instruments' WidebusTM Family
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
  • Typical VOLP (Output Ground Bounce)
    <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)

Widebus is a trademark of Texas Instruments.

  • Members of Texas Instruments' WidebusTM Family
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
  • Typical VOLP (Output Ground Bounce)
    <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)

Widebus is a trademark of Texas Instruments.

The 'ABT16825 devices are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as two 9-bit buffers or one 18-bit buffer. They provide true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 'ABT16825 devices are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as two 9-bit buffers or one 18-bit buffer. They provide true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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기술 자료

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19개 모두 보기
유형 직함 날짜
* Data sheet 18-Bit Buffers/Drivers 18-Bit Buffers/Drivers With 3-State Outputs datasheet (Rev. D) 2000/10/03
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 2004/02/16
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997/03/01
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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시뮬레이션 모델

SN74ABT16825 Behavioral SPICE Model

SCBM148.ZIP (7 KB) - PSpice Model
패키지 CAD 기호, 풋프린트 및 3D 모델
SSOP (DL) 56 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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