SN74ABTE16246
- Member of the Texas Instruments Widebus™ Family
- Supports the VME64 ETL Specification
- Reduced TTL-Compatible Input Threshold Range
- High-Drive Outputs (IOH = –60 mA, IOL = 90 mA) Support Equivalent 25-
Incident-Wave Switching - VCC BIAS Pin Minimizes Signal Distortion During Live Insertion
- Internal Pullup Resistor on OE\ Keeps Outputs in High-Impedance State During Power Up or Power Down
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Equivalent 25- Series Damping Resistor on B Port
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Widebus is a trademark of Texas Instruments.
The SN74ABTE16246 is an 11-bit noninverting transceiver designed for asynchronous two-way communication between buses. This device has open-collector and 3-state outputs. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated. When OE\ is low, the device is active.
The B port has an equivalent 25- series output resistor to reduce ringing. Active bus-hold inputs on the B port hold unused or floating inputs at a valid logic level.
The A port provides for the precharging of the outputs via VCCBIAS, which establishes a voltage between 1.3 V and 1.7 V when VCC is not connected.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN74ABTE16246 datasheet (Rev. J) | 2003/08/06 | |
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Selection guide | Advanced Bus Interface Logic Selection Guide | 2001/01/09 | ||
| Application note | Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) | 1996/12/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SSOP (DL) | 48 | Ultra Librarian |
| TSSOP (DGG) | 48 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치