SN74ALS642A-1
- Bidirectional Bus Transceivers in High-Density 20-Pin Packages
- Choice of True or Inverting Logic
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs
These octal bus transceivers are designed for asynchronous two-way communication between
data buses. These devices transmit data from the A bus to the B
bus or from the B bus to the A bus, depending upon the level at the
direction-control (DIR) input. The output-enable input disables the device so that
the buses are effectively isolated.
The -1 versions of the SN74ALS641A and SN74ALS642A are identical to the standard versions, except that the recommended maximum IOL is increased to 48 mA in the -1 versions.
The SN74ALS641A, SN74ALS642A, and SN74AS641 are characterized for operation from 0°C to 70°C.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | Octal Bus Transceivers With Open-Collector Outputs datasheet | 1995/03/01 | |
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997/08/01 | ||
Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 | ||
Application note | Live Insertion | 1996/10/01 | ||
Application note | Advanced Schottky (ALS and AS) Logic Families | 1995/08/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
PDIP (N) | 20 | Ultra Librarian |
SOIC (DW) | 20 | Ultra Librarian |
SOP (NS) | 20 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치