홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 범용 트랜시버
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버퍼, 드라이버 및 트랜시버
범용 트랜시버

SN74ALVTH16601

구형

3상 출력을 지원하는 2.5V/3.3V 18비트 범용 버스 트랜시버

지금 주문
데이터 시트
SN74ALVTH16601은(는) 더 이상 생산되지 않습니다.
이 제품은 더 이상 생산되지 않습니다. 새로운 설계는 대체 제품을 고려해야 합니다.
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비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74ALVCH16601 활성 3상 출력을 지원하는 18비트 범용 버스 트랜시버 Replacement

SN74ALVTH16601

구형
데이터 시트 지금 주문

제품 상세 정보

Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Technology family ALVT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Technology family ALVT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TVSOP (DGV) 56 72.32 mm² 11.3 x 6.4
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
  • State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • High-Drive (-24/24 mA at 2.5-V and
    -32/64 mA at 3.3-V VCC)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
  • Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
  • Flow-Through Architecture Facilitates Printed Circuit Board Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR and
the DGVR package is abbreviated to VR.
UBT and Widebus are trademarks of Texas Instruments Incorporated.
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
  • State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • High-Drive (-24/24 mA at 2.5-V and
    -32/64 mA at 3.3-V VCC)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
  • Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
  • Flow-Through Architecture Facilitates Printed Circuit Board Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR and
the DGVR package is abbreviated to VR.
UBT and Widebus are trademarks of Texas Instruments Incorporated.

The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ALVTH16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16601 is characterized for operation from -40°C to 85°C.

The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ALVTH16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16601 is characterized for operation from -40°C to 85°C.
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유형 직함 날짜
* Data sheet 2.5-V/3.3-V 18-Bit Universal Bus Transceiver With 3-State Outputs datasheet (Rev. A) 1999/07/12

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치