홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 범용 트랜시버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
범용 트랜시버

SN74AVC16834

활성

3상 출력을 지원하는 18비트 범용 버스 드라이버

지금 주문
데이터 시트

SN74AVC16834

활성
데이터 시트 지금 주문

제품 상세 정보

Supply voltage (min) (V) 1.4 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 12 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family AVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.4 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 12 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family AVC Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1 TVSOP (DGV) 56 72.32 mm² 11.3 x 6.4
  • Member of the Texas Instruments Widebus™ Family
  • DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

DOC and Widebus are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

DOC and Widebus are trademarks of Texas Instruments.

A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.

This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.

This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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기술 자료

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13개 모두 보기
유형 직함 날짜
* Data sheet 18-Bit Universal Bus Driver With 3-State Outputs datasheet (Rev. H) 2002/02/12
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015/04/30
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
More literature LCD Module Interface Application Clip 2003/05/09
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002/08/20
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999/07/07
Application note AVC Logic Family Technology and Applications (Rev. A) 1998/08/26

설계 및 개발

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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
TSSOP (DGG) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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