제품 상세 정보

Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Operating Voltage Range of 4.5 V to 5.5 V
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads
  • Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs)

  • Operating Voltage Range of 4.5 V to 5.5 V
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads
  • Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs)

These octal buffers and line drivers are designed to have the performance of the ’HCT240 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.

The 3-state control gate is a 2-input NOR. If either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state. The ’HCT540 devices provide inverted data at the outputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These octal buffers and line drivers are designed to have the performance of the ’HCT240 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.

The 3-state control gate is a 2-input NOR. If either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state. The ’HCT540 devices provide inverted data at the outputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
CD74HCT240 활성 TTL 호환 CMOS 입력 및 3상 출력을 지원하는 8채널 4.5V~5.5V 인버터 Voltage range (4.5V to 5.5V), average drive strength (4mA), average propagation delay (22ns)

기술 자료

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12개 모두 보기
유형 직함 날짜
* Data sheet SN54HCT540, SN74HCT540 datasheet (Rev. C) 2003/03/18
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
시뮬레이션 모델

SN74HCT540 Behavioral SPICE Model

SCLM196.ZIP (7 KB) - PSpice Model
패키지 CAD 기호, 풋프린트 및 3D 모델
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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