SN74LS292

Name: SN74LS292
Brand: TI
SKU: SN74LS292
Price: 14.62 USD

활성

프로그래머블 주파수 디바이더/디지털 타이머

지금 주문

데이터 시트

document-pdfAcrobat SN74LS29x Programmable Frequency Dividers and Digital Timers datasheet (Rev. A) (영어) PDF | HTML

SN74LS292

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

LS

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

0 to 70

Technology family

LS

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

0 to 70

PDIP (N)

16

181.42 mm² 19.3 x 9.4

Count Divider Chain
Digitally Programmable from 2² to 2ⁿ
(n = 31 for SN74LS292 , n = 15 for SN74LS294)
Useable Frequency Range from DC to 30 MHz
Easily Expandable

Count Divider Chain
Digitally Programmable from 2² to 2ⁿ
(n = 31 for SN74LS292 , n = 15 for SN74LS294)
Useable Frequency Range from DC to 30 MHz
Easily Expandable

The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low CLR clear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating.

A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 2¹⁰ gives a period of 1.024 ms, 2²⁰ gives a period of 1.05 sec, 2²⁶ gives a period of 1.12 min, and 2³¹ gives a period of 35.79 min.

These devices are easily cascadable, giving limitless possibilities to achievable timing delays.

The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low CLR clear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating.

A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 2¹⁰ gives a period of 1.024 ms, 2²⁰ gives a period of 1.05 sec, 2²⁶ gives a period of 1.12 min, and 2³¹ gives a period of 35.79 min.

These devices are easily cascadable, giving limitless possibilities to achievable timing delays.

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