SN74LV244AT

Name: SN74LV244AT
Brand: TI
SKU: SN74LV244AT
Price: 0.184 USD

활성

TTL 호환 CMOS 입력 및 3상 출력을 지원하는 8채널 4.5V~5.5V 버퍼

지금 주문

데이터 시트

document-pdfAcrobat SN74LV244AT datasheet (Rev. C) (영어)

SN74LV244AT

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

LV-AT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

16

Supply current (max) (µA)

20

IOH (max) (mA)

-16

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LV-AT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

16

Supply current (max) (µA)

20

IOH (max) (mA)

-16

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

VQFN (RGY)

20

15.75 mm² 4.5 x 3.5

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd = 5.4 ns at 5 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 5 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd = 5.4 ns at 5 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 5 V, T_A = 25°C
Supports Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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