SN74LVC3G34

Name: SN74LVC3G34
Brand: TI
SKU: SN74LVC3G34
Price: 0.113 USD

활성

3채널, 1.65V~5.5V 버퍼

지금 주문

데이터 시트

document-pdfAcrobat SN74LVC3G34 Triple Buffer Gate datasheet (Rev. L) (영어) PDF | HTML

SN74LVC3G34

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

2.8125 mm² 2.25 x 1.25

SSOP (DCT)

11.8 mm² 2.95 x 4

VSSOP (DCU)

6.2 mm² 2 x 3.1

Available in the Texas Instruments
NanoFree Package
Supports 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

Available in the Texas Instruments
NanoFree Package
Supports 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The SN74LVC3G34 device is a triple buffer gate designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC3G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC3G34 device is a triple buffer gate designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC3G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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27개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74LVC3G34 Triple Buffer Gate datasheet (Rev. L)	PDF \| HTML	2015/10/30
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004/11/04
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	User guide	Signal Switch Data Book (Rev. A)		2003/11/14
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		2003/11/06
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		2002/12/18
	Application note	Texas Instruments Little Logic Application Report		2002/11/01
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002/06/13
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		2002/05/22
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		2002/05/10
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		2002/03/27
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		1997/12/01
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		1997/08/01
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997/06/01
	Application note	LVC Characterization Information		1996/12/01
	Application note	Input and Output Characteristics of Digital Integrated Circuits		1996/10/01
	Application note	Live Insertion		1996/10/01
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		1996/09/01
	Application note	Understanding Advanced Bus-Interface Products Design Guide		1996/05/01