홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 비인버팅 버퍼 및 드라이버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
비인버팅 버퍼 및 드라이버

SN74LVCH162244A

활성

버스 홀드 및 3상 출력을 지원하는 16채널, 1.65V~3.6V 버퍼

지금 주문
데이터 시트

SN74LVCH162244A

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 20 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 20 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Member of the Texas Instruments
    Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.4 ns at 3.3 V
  • Output Ports Have Equivalent 26-Ω Series
    Resistors, so No External Resistors are Required
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Member of the Texas Instruments
    Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.4 ns at 3.3 V
  • Output Ports Have Equivalent 26-Ω Series
    Resistors, so No External Resistors are Required
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Supports Mixed-Mode Signal Operation on All Ports
    (5-V Input/Output Voltage With 3.3-V VCC)
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup or Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The SN74LVCH162244A device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

The SN74LVCH162244A device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
filter 기타 비인버팅 버퍼 및 드라이버 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74AUC16244 활성 3상 출력을 지원하는 16채널, 0.8V~2.7V 고속 버퍼 Smaller voltage range (0.8V to 2.7V), shorter average propagation delay (1.7ns)
비교 대상 장치와 유사한 기능
SN74LVC244A 활성 3상 출력을 지원하는 8채널, 1.65V~3.6V 버퍼 Voltage range 1.65V to 3.6V, average propagation delay 5.5ns, average drive strength 24mA

기술 자료

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29개 모두 보기
유형 직함 날짜
* Data sheet SN74LVCH162244A 16-Bit Buffer/Driver with 3-State Outputs datasheet (Rev. L) PDF | HTML 2014/05/02
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018/09/17
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Simultaneous-Switching Performance of TI Logic Devices (Rev. B) 2005/02/23
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

HSPICE MODEL OF SN74LVCH162244A

SCEJ233.ZIP (293 KB) - HSpice Model
다운로드
시뮬레이션 모델

SN74LVCH162244A Behavioral SPICE Model

SCAM096.ZIP (7 KB) - PSpice Model
다운로드
시뮬레이션 모델

SN74LVCH162244A IBIS Model (Rev. B)

SCEM063B.ZIP (45 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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