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SN74LVC1G99-Q1

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Automotive Catalog Ultra-Configurable Multi-Function Gate With 3-State Outputs

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Data sheet

SN74LVC1G99-Q1

ACTIVE
Data sheet Order now

Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Qualified for Automotive Applications
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Low Power Consumption, 15-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Offers Nine Different Logic Functions in a Single Package
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows for Slow Input Transition Time and
    Better Noise Immunity at Input
  • Qualified for Automotive Applications
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Low Power Consumption, 15-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Offers Nine Different Logic Functions in a Single Package
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows for Slow Input Transition Time and
    Better Noise Immunity at Input

The SN74LVC1G99-Q1 is operational from 1.65 V to 5.5 V.

The SN74LVC1G99-Q1 features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent inverter, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC1G99-Q1 is operational from 1.65 V to 5.5 V.

The SN74LVC1G99-Q1 features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent inverter, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Type Title Date
* Data sheet SN74LVC1G99-Q1, Ultra-Configurable Multi-Function Gate With 3-State Outputs datasheet 19 Apr 2011
Application brief Utilizing Configurable Logic in System Design PDF | HTML 30 Oct 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
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Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
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Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
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User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
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Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
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