ADC081500
- Internal Sample-and-Hold
- Single +1.9V ±0.1V Operation
- Choice of SDR or DDR Output Clocking
- Multiple ADC Synchronization Capability
- Ensured No Missing Codes
- Serial Interface for Extended Control
- Fine Adjustment of Input Full-Scale Range and Offset
- Duty Cycle Corrected Sample Clock
Key Specifications
- Resolution 8 Bits
- Max Conversion Rate 1.5 GSPS (min)
- Bit Error Rate 10-18 (typ)
- ENOB @ 748 MHz Input 7.3 Bits (typ)
- DNL ±0.15 LSB (typ)
- Power Consumption
- Operating 1.2 W (typ)
- Power Down Mode 3.5 mW (typ)
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The ADC081500 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.2 W at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.3 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable output offset voltage between 0.8V and 1.2V.
The converter output has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to one-half the sample rate.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | ADC081500 High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter datasheet (Rev. G) | 2013年 4月 18日 | |
EVM User's guide | AN-1615 LMH6555 Evaluation Board (Rev. A) | 2013年 4月 26日 | ||
Application note | Generating Precision Clocks for Time- Interleaved ADCs | 2007年 8月 2日 | ||
White paper | High-Performance Analog Front Ends | 2006年 1月 1日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
HLQFP (NNB) | 128 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點