ADC08B200-Q1
- Single-Ended Input
- Selectable Capture Buffer Size
- PLL for Clock Multiplication
- Reference Ladder Top and Bottom Accessible
- Linear Power Scaling with Sample Rate
- FPGA Training Pattern
- AEC-Q100 Grade 2 Qualified
- Power-Down Feature
Key Specifications
- Resolution 8 Bits
- Maximum Sampling Frequency 200 MSPS (min)
- DNL ±0.4 LSB (typ)
- ENOB (fIN= 49 MHz) 7.2 bits (typ)
- THD (fIN= 49 MHz) −53 dBc (typ)
- Power Consumption
- Operating (50 MHz) Input 2 mW / Msps (typ)
- Power Down 2.15 mW (typ)
(PLL Bypassed)
All trademarks are the property of their respective owners.
The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock.
The ADC08B200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08B200's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 2.7V to 3.3V logic. The digital inputs and outputs are low voltage TTL/CMOS compatible and the output data format is straight binary.
The ADC08B200Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 2 Qualified.
The ADC08B200 is offered in a 48-pin plastic package (TQFP) and is specified over the extended industrial temperature range of −40°C to +105°C. An evaluation board is available to assist in the easy evaluation of the ADC08B200.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | ADC08B200 / ADC08B200Q 8-Bit, 200 MSPS A/D Converter with Capture Buffer datasheet (Rev. F) | 2013年 4月 2日 | |
Application note | Adaptive Speed Control for Automotive Systems | 2007年 11月 20日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TQFP (PFB) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點