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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12QJ800-Q1

現行

具有 JESD204C 介面的車用四通道、12 位元、800-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADC12QJ800-Q1

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 800 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1660 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (Bits) 9 SFDR (dB) 62 Operating temperature range (°C) -40 to 125 Input buffer Yes
Sample rate (max) (Msps) 800 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1660 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (Bits) 9 SFDR (dB) 62 Operating temperature range (°C) -40 to 125 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 800MSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (97MHz): 57.6dBFS
    • ENOB (97MHz): 9 Bits
    • SFDR (97MHz): 62dBFS
    • Noise floor (–20dBFS): –146.1dBFS/Hz
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800MSPS):
    • Quad Channel: 415mW / channel
    • Dual channel: 555mW / channel
    • Single channel: 830mW
  • Power supplies: 1.1V, 1.9V
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 800MSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (97MHz): 57.6dBFS
    • ENOB (97MHz): 9 Bits
    • SFDR (97MHz): 62dBFS
    • Noise floor (–20dBFS): –146.1dBFS/Hz
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800MSPS):
    • Quad Channel: 415mW / channel
    • Dual channel: 555mW / channel
    • Single channel: 830mW
  • Power supplies: 1.1V, 1.9V

ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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* Data sheet ADC12xJ800-Q1 Quad, Dual, Single Channel, 800MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) PDF | HTML 2024年 10月 22日

設計與開發

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開發板

ADC12QJ1600EVM — 具有 JESD204C 介面且適用於四通道、12 位元、1.6GSPS ADC 的 ADC12QJ1600 評估模組

ADC12QJ1600 評估模組 (EVM) 可用於評估 ADC12QJ1600-Q1 產品。ADC12QJ1600-Q1 是一款低功耗、12 位元、四通道、1.6GSPS 類比轉數位轉換器 (ADC)，具有緩衝類比輸入和整合式數位降壓轉換器，附帶具有 JESD204B/C 介面的晶片內建 PLL。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。

EVM 隨附 LMK04828 JESD204B/C 時鐘產生器，並且可配置為提供適用於完整 JESD204B/C 子類別 1 計時解決方案的超低抖動 ADC 裝置時鐘與 SYSREF。

ADC12QJ1600-Q1 和 (...)

使用指南: PDF
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開發板

TSW12QJ1600EVM — ADC12QJ1600-Q1 8 通道 (兩個同步 4 通道) 12 位元 1.6-GSPS JESD204C 介面 ADC 評估模組

TSW12QJ1600 評估模組 (EVM) 用於評估具備不同前端選項的 ADC12QJ1600-Q1 類比轉數位轉換器 (ADC)。ADC12QJ1600-Q1 是一款具有四個類比輸入通道的 12 位元 ADC，能以高達每秒 1.6 千兆取樣率 (GSPS) 運作。

此設計在相同印刷電路板 (PCB) 上有兩項 ADC12QJ1600-Q1 裝置，可用來展示多個 ADC 同步化、決定性延遲，並以各種前端選項 (AC 耦合變壓器；DC 耦合選項與 LMH32401) 測試 ADC 的性能。此設計也示範如何透過菊鏈將 PLL 參考輸出 (PLLREFO+、PLLREFO-) 從一個 ADC (...)

使用指南: PDF
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模擬型號

ADC12QJ1600 IBIS-AMI Model

SBAM512.ZIP (68 KB) - IBIS-AMI Model
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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FCCSP (AAV) 144 Ultra Librarian
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