ADC14L020
- Single +3.3V Supply Operation
- Internal Sample-and-Hold
- Internal Reference
- Outputs 2.4V to 3.6V Compatible
- Duty Cycle Stabilizer
- Power Down Mode
Key Specifications
- Resolution 14 Bits
- DNL ±0.5 LSB (typ)
- SNR (fIN = 10 MHz) 74 dB (typ)
- SFDR (fIN = 10 MHz) 93 dB (typ)
- Data Latency 7 Clock Cycles
- Power Consumption
- Operating 150 mW (typ)
- Power Down Mode 15 mW (typ)
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The ADC14L020 is a low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at 20 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 150 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC14L020 achieves 12.0 effective bits at nyquist and consumes just 150 mW at 20 MSPS . The Power Down feature reduces power consumption to 15 mW.
The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.
To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC14L020 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage.
This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | ADC14L020 14-Bit, 20 MSPS, 150 mW A/D Converter datasheet (Rev. D) | 2013年 4月 19日 | |
User guide | ADC14L020/ADC14L040 14-Bit, 20/40 Msps, 3.3V, 150/235 mW ADC User Guide | 2012年 2月 21日 | ||
White paper | Intermediate Frequency (IF) Sampling Receiver Concepts | 2006年 5月 31日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
LQFP (NEY) | 32 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
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