CD4066B
- 15V digital or ±7.5V peak-to-peak switching
- 125Ω typical on-state resistance for 15V operation
- Switch on-state resistance matched to within 5Ω over 15V signal-input range
- On-state resistance flat over full peak-to-peak signal range
- High on or off output-voltage ratio: 80dB typical at fis = 10kHz, RL = 1kΩ
- High degree of linearity: <0.5% distortion typical at fis = 1kHz, Vis = 5Vp-p VDD – VSS ≥ 10V, RL = 10kΩ
- Extremely low off-state switch leakage, resulting in very low offset current and high effective off-state resistance: 10 pA typical at VDD – VSS = 10V, TA = 25°C
- Extremely high control input impedance (control circuit isolated from signal circuit): 1012Ω typical
- Low crosstalk between switches: –50dB typical at fis = 8MHz, RL = 1kΩ
- Matched control-input to signal-output capacitance: reduces output signal transients
- Frequency response, switch On = 40MHz typical
- 100% tested for quiescent current at 20V
- 5V, 10V, and 15V parametric ratings
The CD4066B device is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B device, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range.
The CD4066B device consists of four bilateral switches, each with independent controls. Wide operating supply of 3V to 18V allows for use in a broad array of applications. The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B device is recommended.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CD4066B CMOS Quad Bilateral Switch datasheet (Rev. J) | PDF | HTML | 2024年 8月 9日 |
| Application note | Selecting the Correct Texas Instruments Signal Switch (Rev. E) | PDF | HTML | 2022年 6月 2日 | |
| Application note | Multiplexers and Signal Switches Glossary (Rev. B) | PDF | HTML | 2021年 12月 1日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| User guide | Signal Switch Data Book (Rev. A) | 2003年 11月 14日 | ||
| Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001年 12月 3日 |
設計與開發
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LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| PDIP (N) | 14 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。