產品詳細資料

Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Power supply voltage - dual (V) +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 30 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 6 Supply voltage (max) (V) 10 Negative rail supply voltage (max) (V) 0
Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Power supply voltage - dual (V) +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 30 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 6 Supply voltage (max) (V) 10 Negative rail supply voltage (max) (V) 0
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Wide analog-input-voltage range:

    VCC - VEE: 0V to 10V

  • Low ON resistance:
    • 45Ω (typical): VCC = 4.5V
    • 35Ω (typical): VCC = 6V
    • 30Ω (typical): VCC – VEE = 9V
  • Fast switching and propagation delay times
  • Low OFF leakage current
  • Built-in break-before-make switching
  • Logic-level translation to enable 5V logic to accommodate ±5 V analog signals
  • Wide operating temperature range: -55°C to 125°C
  • HC types:
    • 2V to 10V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT types:
    • Direct LSTTL input logic compatibility, VIL= 0.8V (maximum), VIH = 2V (minimum)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH
  • Wide analog-input-voltage range:

    VCC - VEE: 0V to 10V

  • Low ON resistance:
    • 45Ω (typical): VCC = 4.5V
    • 35Ω (typical): VCC = 6V
    • 30Ω (typical): VCC – VEE = 9V
  • Fast switching and propagation delay times
  • Low OFF leakage current
  • Built-in break-before-make switching
  • Logic-level translation to enable 5V logic to accommodate ±5 V analog signals
  • Wide operating temperature range: -55°C to 125°C
  • HC types:
    • 2V to 10V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT types:
    • Direct LSTTL input logic compatibility, VIL= 0.8V (maximum), VIH = 2V (minimum)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH

The ’HC4316 and CD74HCT4316 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

In addition these devices contain logic-level translation circuits that provide for analog signal switching of voltages between ±5V via 5V logic. Each switch is turned on by a high-level voltage on its select input (S) when the common Enable (E) is Low. A High E disables all switches. The digital inputs can swing between VCC and GND; the analog inputs/outputs can swing between VCC as a positive limit and VEE as a negative limit. Voltage ranges are shown in Figure 13-1 and Figure 13-2.

The ’HC4316 and CD74HCT4316 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

In addition these devices contain logic-level translation circuits that provide for analog signal switching of voltages between ±5V via 5V logic. Each switch is turned on by a high-level voltage on its select input (S) when the common Enable (E) is Low. A High E disables all switches. The digital inputs can swing between VCC and GND; the analog inputs/outputs can swing between VCC as a positive limit and VEE as a negative limit. Voltage ranges are shown in Figure 13-1 and Figure 13-2.

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類型 標題 日期
* Data sheet CDx4HCx4316 High-Speed CMOS Logic Quad Analog Switch with Level Translation datasheet (Rev. E) PDF | HTML 2024年 7月 16日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

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