CD74HC4316
- Wide analog-input-voltage range:
VCC - VEE: 0V to 10V
- Low ON resistance:
- 45Ω (typical): VCC = 4.5V
- 35Ω (typical): VCC = 6V
- 30Ω (typical): VCC – VEE = 9V
- Fast switching and propagation delay times
- Low OFF leakage current
- Built-in break-before-make switching
- Logic-level translation to enable 5V logic to accommodate ±5 V analog signals
- Wide operating temperature range: -55°C to 125°C
- HC types:
- 2V to 10V operation
- High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT types:
- Direct LSTTL input logic compatibility, VIL= 0.8V (maximum), VIH = 2V (minimum)
- CMOS input compatibility, II ≤ 1 µA at VOL, VOH
The ’HC4316 and CD74HCT4316 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
In addition these devices contain logic-level translation circuits that provide for analog signal switching of voltages between ±5V via 5V logic. Each switch is turned on by a high-level voltage on its select input (S) when the common Enable (E) is Low. A High E disables all switches. The digital inputs can swing between VCC and GND; the analog inputs/outputs can swing between VCC as a positive limit and VEE as a negative limit. Voltage ranges are shown in Figure 13-1 and Figure 13-2.
技術文件
設計與開發
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LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
PDIP (N) | 16 | Ultra Librarian |
SOIC (D) | 16 | Ultra Librarian |
SOP (NS) | 16 | Ultra Librarian |
TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。