開發模組 (EVM) 的 GUI
CDCE62002
- Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter
- Fully Configurable Outputs Including Frequency and Output Format
- Smart Input Multiplexer Automatically Switches Between One of Two Reference Inputs
- Multiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover Mode
- Integrated EEPROM Determines Device Configuration at Power Up
- Excellent Jitter Performance
- Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:
- Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode
- Programmable Charge Pump Gain and Loop Filter Settings
- Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.
- Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:
- 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
- Low Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHz
- Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode
- LVPECL, LVDS, and LVCMOS
- Independent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32
- Flexible Inputs With Innovative Smart Multiplexer:
- Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)
- One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHz
- Clock Generator Mode Using Crystal Input
- Smart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe Operation
- Typical Power Consumption 750 mW at 3.3 V
- Integrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined State
- Offered in QFN-32 Package
- ESD Protection Exceeds 2000 V HBM
- Industrial Temperature Range: –40°C to +85°C
- APPLICATIONS
- Data Converter and Data Aggregation Clocking
- Wireless Infrastructure
- Switches and Routers
- Medical Electronics
- Military and Aerospace
- Industrial
- Clock Generation and Jitter Cleaning
All other trademarks are the property of their respective owners
The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS(1).
It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
(1) 10-kHz to 20-MHz integration bandwidth.
(2) Frequency range depends on operational mode and output format selected.
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 3 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCE62002 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs datasheet (Rev. E) | PDF | HTML | 2016年 10月 9日 |
| White paper | Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) | PDF | HTML | 2024年 4月 30日 | |
| User guide | Two/Four Output Low Noise Clock Evaluation Board | 2009年 6月 19日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
CDCE62002EVM — CDCE62002 評估模組
CDCE62002EVM is the evaluation module for CDCE62002. The CDCE62002 is a high performance clock generator featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. The CDCE62002 achieves jitter performance under (...)
使用指南: PDF
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。